Name: Simultaneous Multithreading with RISC-V Enables Higher Throughput Efficiency in Data-Centric Applications in Automotive - Vasanth Waran, MIPS
Start: 2024-10-23T14:55:00-0700
End: 2024-10-23T15:13:00-0700

October 22-23, 2024
Santa Clara, CA
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Wednesday October 23, 2024 2:55pm - 3:13pm PDT

Grand Ballroom H (Level 1)

This session covers how simultaneous multithreading (SMT) with RISC-V Hardware threads (harts) increases the throughput efficiency of a processing subsystem for automotive applications.

Speakers

Vasanth Waran

Head of Automotive Business Unit, MIPS

Vasanth Waran heads the Automotive Business unit at MIPS. He has 22 years of experience in the Semiconductor industry and spend a majority of his career at Intel Corporation and Qualcomm Inc, in various roles from Design Engineering, Product development, Platform Applications and... Read More →

Wednesday October 23, 2024 2:55pm - 3:13pm PDT
Grand Ballroom H (Level 1)

HPC / Data Center

Audience Experience Level Beginner

RISC-V Summit

Vasanth Waran

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